The present invention relates to integrated circuits, and, more particularly, to a method of page mode writing in an electrically erasable and programmable memory in which several words can be written in memory in a single access operation. The present invention also relates to an architecture corresponding to this method. The present invention may be applied especially to EEPROM type memories, and more generally, to memories offering a method of writing in the page mode.
Commonly used memory architectures provide for reading or writing of information encoded using several bits, e.g., bytes (eight bits), for forming information words. In this case, the memory array is organized in columns. Each column groups eight bit lines B10-B17 together. Thus, it is possible to simultaneously access eight memory cells located on the same row that contain corresponding information bits D0-D7. All the cells of the same column are connected to a source line.
The selection of a given memory cell requires the application of appropriate levels of voltage to a row, column, bit line and source line depending on the operation to be performed on the memory cell. The operation may be a read, erase (writing of a 1) or programming (writing of a 0) operation. A programming operation requires a preliminary erase operation. Depending on the acess specifications to the memory, a design engineer has several architecture possibilities to choose from. A well-known exemplary architecture is illustrated in FIG. 1.
In this example, the memory array is organized in p+1 rows Wl0 to Wlp, and m+1 columns Col0 to Colm. For each of these columns, there are associated eight bit lines Bl0 to B17 therewith. Each word in the memory has eight cells C0, . . . , C7 placed in the same row.
The memory word M0 corresponding to the row Wl0 and the column Col0 is illustrated in detail in FIG. 1. There are eight memory cells C0 to C7. Each of the cells has an access transistor Ta series-connected with a floating-gate transistor Tf. The access transistor Ta is connected at its gate to the corresponding row Wl0, and at its drain to the corresponding bit line. For example, bit line Bl0 is connected to cell C0.
An additional access transistor Tc0,0 has its gate connected to the corresponding row Wl0 and its drain connected to the corresponding column Col0. Its source is connected to the control gate of each of the floating-gate transistors Tf of the cells C0 to C7 of the word considered. Finally, the sources of these transistors Tf are connected together to a source line S10 associated with the column Col0. In the example, there is one source line S10, . . . , Slm per column Col0, . . . , Colm of the memory array.
In the invention, special attention is paid to a memory access mode in which the memory can be written in page by page. Each page corresponds to a group of words of the memory. In the prior art, each page corresponds to a row of the memory array. In the example, there are therefore p+1 pages corresponding to the p+1 rows Wl0 to Wlp.
To summarize, in page mode, it is sufficient for a user to present the address of the page to be written on the external address bus, and then successively present all the data to be written on the external data bus of the memory circuit. Specific internal circuits of the memory circuit then perform the sequencing operations needed to erase and program the memory cells of the addressed page.
In particular, these internal circuits comprise a temporary memory to store the data to be written. The elements of this temporary memory are generally bistable circuits, and are also known as latches. The page mode write circuit thus requires at least as many latches as there are data bits to be written in a page, and additional circuits to apply appropriate levels of voltage to the cells depending on the contents of these latches. The erasure and programming operations require the use of a high voltage applied appropriately to one or more of the access lines to the cells, especially the bit columns and the bit lines.
In particular, these write circuits have to apply a high voltage to those bit lines of the memory array in which a data element is to be written (erasure operation). The temporary memory must furthermore comprise one additional latch per column, enabling also the application of the high voltage to the columns of the memory. This is necessary to obtain the operation for the erasure of the cells before they are programmed.
For these various reasons, all the elements of the temporary memory are high-voltage type elements by which the high voltage can be switched over to the bit lines and the columns. FIG. 1 thus shows a prior art architecture with the elements affected by the page write mode, especially the temporary memory.
This architecture shows the typical circuits enabling read and write access to the memory. There is thus an address register 1 receiving the address signals A0-AK from the external address bus and giving internal address signals ADRX, ADRY to the different decoding circuits. A data register 2 receives the external input/output data signals D0-D7 from the external data bus. This data register internally delivers data signals Di0-Di7 corresponding to the external data that it receives. It receives output data signals Ds0-Ds7 internally from the read amplifier circuit 3 of the non-volatile memory.
A logic circuit 4 for the general control of the memory appropriately controls the different internal circuit elements. These elements include the row decoder DECX and the associated high-voltage selector switch HVX, the column decoder DECY, the read amplifier circuit 3, the high-voltage Vpp generator HVGEN, the generator of phasing logic signals CLKGEN, and the high-voltage type temporary memory HMT, etc. The logic circuit 4 controls these different circuit elements as a function of the external signals that it receives. These signals include the pack selection control signal /CE, data output enabling signals /OE, and write signals /WE.
To access the array 5 of memory cells, the circuit usually comprises a row decoder DECX to select one row among the rows Wl0-Wlp of the memory array, and a column decoder DECY to select one or more columns Col0-Colm of the memory array. The row decoder provides selection logic signals Row0, . . . , Rowp to the high voltage selector switch HVX which, at output, applies the appropriate voltage levels to the rows as a function of the access mode. The column decoder DECY provides selection logic signals Selcol0, . . . , Selcolm. These signals are applied to a read gate circuit 8 to connect a group of bit lines Bl0, . . . , Bl7 to the read amplifier circuit 3. In the example, these column selection signals are also applied to the temporary memory.
The temporary memory, referenced HMT, can store m+1 words MI0 to MIm corresponding to a page of the memory, namely one information word per column. Each information word MIi comprises an information bit for the selection of the corresponding column, and eight information bits corresponding to the data element to be written. The column selection information bits are given by the column selection signals SelCol0 to SelColm and are output by the column decoder DECY. The eight other information bits are given by the internal data input bus via signals Di0 to Di7. In the example, the temporary memory therefore comprises (9*m+1) high-voltage latches. If m=15, which is typical for a memory having a capacity of 2 kilobytes with 16 rows and 16 columns, there are 144 high-voltage latches.
For writing in the non-volatile memory as a function of the information words previously registered in the latches of the memory HMT, these latches are controlled by a high-voltage control signal CGT given by the phase signals generation circuit CLKGEN. Thus, the programming voltage is applied to all the bit lines. The page mode thus enables the writing of m+1 words of the memory in a period of time equal to only one period needed to write a single memory cell. This is very useful, for example, in applications where a large amount of data has to be written periodically.
However, the high-voltage latches are elements whose physical layout in an integrated circuit uses a lot of space. For example, in a memory circuit with a memory capacity of 2 kilobytes, the high-voltage latches needed to implement the page mode take as much space on the circuit as the memory array itself. This is a major drawback, especially for making low-capacity memory circuits (2 kilobytes) at low cost.
U.S. Pat. No. 5,363,330 discloses an architecture in which the high-voltage latches of the temporary memory are replaced by low-voltage latches, which are less bulky. Writing is done by an appropriate sequencing of high-voltage translators and high-voltage multiplexers. This architecture reduces the amount of space taken up by the memory, but the writing time is appreciably longer.
In view of the foregoing background, it is therefore an object of the present invention is to reduce the number of high-voltage latches needed to implement the page mode.
This and other objects, features, and advantages in accordance with the present invention are provided by changing the page mode concept. According to the present invention, a page no longer corresponds to a row of the memory, but to a column. This change in the concept of the page mode associated with a temporary memory powered at the logic supply voltage, and no longer at high voltage, achieves the goals of reducing the cost of the concerned memories without excessively penalizing the page mode access time.
A method of writing in page mode in an electrically erasable and programmable non-volatile memory in an integrated circuit is thus provided. The memory comprises a memory array organized in matrix form in columns and rows of memory words. Each memory word comprises a plurality of memory cells. Each memory cell is associated with a bit line, a row decoder and a column decoder respectively providing row selection signals and column selection signals enabling the application of appropriate voltage levels for read access and write access to the memory array. Page mode write means comprises a temporary memory to store data to be written in the page.
The method comprises an initialization phase comprising the writing of an information element for the selection of the page to be written in a storage latch associated with a column of the non-volatile memory array, and the writing in a temporary memory of the data to be written in the page. A write phase comprises selecting rows of the non-volatile memory array as a function of the contents of the temporary memory.
The present invention also relates to an architecture of an electrically erasable and programmable non-volatile memory in an integrated circuit, wherein the page mode write means comprises one latch per column of the non-volatile memory array to contain a page selection information element and a control logic circuit. This provides the row selection signals as a function of the contents of the temporary memory in a step for the writing of the column of the non-volatile memory array.